High-speed Image Acquisition and Network Transmission System Based on FPGA

DOI

10.2991/icemie-16.2016.18How to use a DOI?

Keywords

FPGA; Ethernet; Image acquisition; Master computer; Labview

Abstract

Through the study of the Camera Link interface protocol, the Ethernet protocol, and the VGA display sequence, the writer designs a high-speed image acquisition and network transmission system based on FPGA (Field-Programmable Gate Array) CMOS (Complementary Metal Oxide Semiconductor) and details the system structure as well. The system uses FPGA to drive CMOS image sensor for collecting the image data, and DDR3 module for data caching. Through controlling the Ethernet interface chip by the FPGA master control chip, the systems can achieve high-speed data transmission and transmit the image data to the upper computer for display or to the VGA (Video Graphics Array) for display on the screen. The system achieves high-speed image data acquisition, storage, remote transmission and display.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Hao Wang
AU  - Zhi Weng
AU  - Xiaochun Li
PY  - 2016/04
DA  - 2016/04
TI  - High-speed Image Acquisition and Network Transmission System Based on FPGA
BT  - Proceedings of the 2016 International Conference on Electrical, Mechanical and Industrial Engineering
PB  - Atlantis Press
SP  - 72
EP  - 75
SN  - 2352-5401
UR  - https://doi.org/10.2991/icemie-16.2016.18
DO  - 10.2991/icemie-16.2016.18
ID  - Wang2016/04
ER  -