DPN Treatment plus Annealing Temperatures for 28nm HK/MG nMOSFETs with CHC Stress
Authors
Mu-Chun Wang, Shea-Jue Wang, Chii-Wen Chen, Hui-Yun Bor, Zhi-Hong Xu, Wen-How Lan
Corresponding Author
Mu-Chun Wang
Available Online April 2016.
- DOI
- 10.2991/icemie-16.2016.19How to use a DOI?
- Keywords
- hot carrier stress; drive current; high-k; MOSFET; anneal; metal-gate; DPN
- Abstract
The possible nano-crystallization formation and thicker interface layer at the higher annealing atmosphere, however, is easy to suppress the superiority of high-k dielectric deposition in the improvement of drive current and reliability. This phenomenon was apparently observed at 900oC annealing tested devices after the nitridation process. The drive current at 900oC annealing before hot-carrier stress is lower than that at 700oC with the same nitrogen concentration and the same feature sizes. After the hot-carrier stress test at 125oC ambience, the degradation of the threshold voltage shift at 900oC is still the worst among all of tested samples.
- Copyright
- © 2016, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Mu-Chun Wang AU - Shea-Jue Wang AU - Chii-Wen Chen AU - Hui-Yun Bor AU - Zhi-Hong Xu AU - Wen-How Lan PY - 2016/04 DA - 2016/04 TI - DPN Treatment plus Annealing Temperatures for 28nm HK/MG nMOSFETs with CHC Stress BT - Proceedings of the 2016 International Conference on Electrical, Mechanical and Industrial Engineering PB - Atlantis Press SP - 76 EP - 80 SN - 2352-5401 UR - https://doi.org/10.2991/icemie-16.2016.19 DO - 10.2991/icemie-16.2016.19 ID - Wang2016/04 ER -