An Efficient Timing Optimization Method in ASIC Design

DOI

10.2991/wartia-17.2017.44How to use a DOI?

Keywords

Clock tree synthesis,Clock skew,Useful clock skew.

Abstract

In the physical design of integrated circuits, the traditional clock tree synthesis is difficult to meet the timing convergence requirements at high frequency. This paper takes a data processing chip design based on TSMC 65nm 1P8M process as an example, proposes a clock tree synthesis method combining bottom-up timing convergence and useful clock skew, efficient to solving the setup time violations of chip at high frequency applications, and meeting the setting time of 0.5ns, holding time 0.15ns, effectively guarantee the timing convergence of the chip.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xu Huang
AU  - Xin He
AU  - Wu Yang
AU  - Yujing Li
PY  - 2017/11
DA  - 2017/11
TI  - An Efficient Timing Optimization Method in ASIC Design
BT  - Proceedings of the 3rd Workshop on Advanced Research and Technology in Industry (WARTIA 2017)
PB  - Atlantis Press
SP  - 219
EP  - 223
SN  - 2352-5401
UR  - https://doi.org/10.2991/wartia-17.2017.44
DO  - 10.2991/wartia-17.2017.44
ID  - Huang2017/11
ER  -