Clock Tree Synthesis and Optimization of SoCs under Low Voltage

DOI

10.2991/wartia-17.2017.43How to use a DOI?

Keywords

Clock Tree Synthesis, Low Voltage, PVT variation

Abstract

With the development of integrated circuits, the power consumption becomes a key problem in the design of integrated circuits. Reducing the operating voltage is an effective way to reduce power consumption. But the chip working voltage is reduced, brings more challenges to the chip design, which is mainly composed of process, voltage and temperature (PVT) variation instability on the performance of chips. According to the problem of clock tree network structure under low voltage, this paper puts forward a method of resistance process, voltage and temperature (PVT) variation clock tree design under low voltage, enhancing the stability of the chip, and ensuring the effectiveness of low voltage design.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xin He
AU  - Xu Huang
AU  - Wu Yang
AU  - Yujing Li
PY  - 2017/11
DA  - 2017/11
TI  - Clock Tree Synthesis and Optimization of SoCs under Low Voltage
BT  - Proceedings of the 3rd Workshop on Advanced Research and Technology in Industry (WARTIA 2017)
PB  - Atlantis Press
SP  - 214
EP  - 218
SN  - 2352-5401
UR  - https://doi.org/10.2991/wartia-17.2017.43
DO  - 10.2991/wartia-17.2017.43
ID  - He2017/11
ER  -