The Assessment and Analysis About the Superiority of VHDL Language on FPGA Design and Development

DOI

10.2991/iwmecs-15.2015.29How to use a DOI?

Keywords

VHDL, FPGA design, assessment, simulation

Abstract

This paper is based on the effect that VHDL language on FPGA design and development, and we design the DDS module of FPGA by using the methods of designing. By research and analyse the The design of DDS module based on FPGA, we learn more about FPGA, visually and concretely. Also, We put forward the MidFilter based on VHDL language. The experiments show that the method can reduce deviation and improve the accuracy of the design.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xuqing Luan
PY  - 2015/10
DA  - 2015/10
TI  - The Assessment and Analysis About the Superiority of VHDL Language on FPGA Design and Development
BT  - Proceedings of the 2015 2nd International Workshop on Materials Engineering and Computer Sciences
PB  - Atlantis Press
SP  - 153
EP  - 158
SN  - 2352-538X
UR  - https://doi.org/10.2991/iwmecs-15.2015.29
DO  - 10.2991/iwmecs-15.2015.29
ID  - Luan2015/10
ER  -