A Design and Performance Evaluation of Dynamically Self-Reconfigurable System Based on Virtex5
- DOI
- 10.2991/isrme-15.2015.66How to use a DOI?
- Keywords
- FPGA; dynamic partial reconfiguration; Virtex-5; time-consuming model
- Abstract
Facing with limitation of hardware resources and increasingly requirements of processing ability, reconfigurable computing technology has become an inevitable trend in compute-intensive system. Dynamic and Partial Reconfiguration (DPR) is a special feature embedded in Field Programmable Gate Arrays (FPGAs), giving designer the ability to reconfigure a certain portion of the FPGA during run-time without influencing the other parts. This paper makes an analysis of time consumption of FPGA-based dynamic reconfiguration and proposes a piecewise reconfigurable system time-consuming model for Xilinx Virtex-5, and then analyzes and obtains the time-consuming parameters of each stage. In addition, an entire time-consuming calculation formula of reconfiguration process is introduced by combining all stages formulas. The experiments results indicate that calculation formula error rate of the reconfiguration time-consuming model is less than 10%, and which can verify the accuracy of the formula.
- Copyright
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Liang Zhang AU - Peiyi Shen AU - Yuxin Cai AU - Jingwen Liu AU - Juan Song PY - 2015/04 DA - 2015/04 TI - A Design and Performance Evaluation of Dynamically Self-Reconfigurable System Based on Virtex5 BT - Proceedings of the 2015 International Conference on Intelligent Systems Research and Mechatronics Engineering PB - Atlantis Press SP - 293 EP - 302 SN - 1951-6851 UR - https://doi.org/10.2991/isrme-15.2015.66 DO - 10.2991/isrme-15.2015.66 ID - Zhang2015/04 ER -