A High Speed Amplifier Used in High-resolution GSPS Pipelined ADC
Authors
Liang Li, Mingyuan Xu, Yong Zhang, Dongbin Fu, Xiaofeng Shen, Xingfa Huang, Jie Pu, Xi Chen
Corresponding Author
Liang Li
Available Online May 2018.
- DOI
- 10.2991/icmse-18.2018.66How to use a DOI?
- Keywords
- ADC, High Speed Amplifier, Gain, Phase Margin, Positive Feedback, CMOS;
- Abstract
In this paper, a high speed amplifier used in high-resolution GSPS pipelined ADC is described. To satisfy a 14bit 1GSPS ADC accuracy and speed demand, The high speed amplifier adopts two-stage Miller compensation architecture. To increase amplifier gain, active gain-boosted cascodes and cross-coupling positive feedback are used in the first stage of the amplifier. To improve phase margin and settling of the amplifier, big resistor and inductor are used in the second stage of the amplifier. The high speed amplifier used in a 14bit 1GSPS pipelined ADC fabricated on a 65nm CMOS process achieves a closed loop gain of 82dB, a closed bandwidth of 4.0GHz, phase margin of 70 degree, dissipates 250mW power, occupys 0.11mm2 area.
- Copyright
- © 2018, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Liang Li AU - Mingyuan Xu AU - Yong Zhang AU - Dongbin Fu AU - Xiaofeng Shen AU - Xingfa Huang AU - Jie Pu AU - Xi Chen PY - 2018/05 DA - 2018/05 TI - A High Speed Amplifier Used in High-resolution GSPS Pipelined ADC BT - Proceedings of the 2018 8th International Conference on Manufacturing Science and Engineering (ICMSE 2018) PB - Atlantis Press SP - 340 EP - 344 SN - 2352-5401 UR - https://doi.org/10.2991/icmse-18.2018.66 DO - 10.2991/icmse-18.2018.66 ID - Li2018/05 ER -