FPGA-Based Research on The Hardware Design of CAVLC Encoder

DOI

10.2991/icibet.2013.78How to use a DOI?

Abstract

H.264/AVC video coding standard adopt CAVLC (Context-based Adaptive Varia-ble Length Coding) in Baseline profile and Extended profile, this paper briefly introduces the principle of CAVLC en-coding; In the hardware design, the Ping-Pong operation and structure of parallel processing are adopted in order to reduce CAVLC encoded clock cycle and im-prove the throughput. All hardware cir-cuits are described by Verilog HDL, and are simulated by using Modelsim SE 6.5, and are verified by using ALTERA Cy-clone II EP2C35F672C8 FPGA.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Jin Xu
AU  - Jianhua Mao
PY  - 2013/03
DA  - 2013/03
TI  - FPGA-Based Research on The Hardware Design of CAVLC Encoder
BT  - Proceedings of the 2013 International Conference on Information, Business and Education Technology (ICIBET 2013)
PB  - Atlantis Press
SP  - 356
EP  - 359
SN  - 1951-6851
UR  - https://doi.org/10.2991/icibet.2013.78
DO  - 10.2991/icibet.2013.78
ID  - Xu2013/03
ER  -