Design and Implementation of a Quadruple Floating-point Fused Multiply-Add Unit

DOI

10.2991/iccsee.2013.438How to use a DOI?

Keywords

floating-point arithmetic, fused multiply-add, quadruple precision, high precision

Abstract

High precision and high performance floating-point unit is an important research object of high performance microprocessor design. According to the characteristic of quadruple precision (QP) floating-point data format and research on double precision floating-point fused multiply-add (FMA) algorithms, a high performance QPFMA is designed and realized, which supports multiple floating-point arithmetic with a 7 cycles pipeline. By adopting dual adder and improving on algorithm architecture, optimizing leading zero anticipation and normalization shifter logic, the latency and hardware cost is decreased. Based on 65nm technology, the synthesis results show that the QPFMA can work at 1.2GHz, with the latency decreased by 3 cycles, the gate number reduced by 18.77% and the frequency increased about 11.63% comparing to current QPFMA design, satisfying the requirements of high performance processor design.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Jun He
AU  - Ying Zhu
PY  - 2013/03
DA  - 2013/03
TI  - Design and Implementation of a Quadruple Floating-point Fused Multiply-Add Unit
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 1749
EP  - 1753
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.438
DO  - 10.2991/iccsee.2013.438
ID  - He2013/03
ER  -