Low-Power Near-threshold MOS Current Mode Logic with Power-Gating Techniques

DOI

10.2991/iccsee.2013.424How to use a DOI?

Keywords

lowe power, power-gating, current mode logic, near-threshold

Abstract

MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, the large static power dissipation of MCML circuit limits its application in portable devices. In this work, we proposed a power-gating (PG) technique to reduce the standby power of the near-threshold MCML. The PG 1-bit full adder and a mod-10 counter are designed and simulated using HSPICE at 45nm CMOS technology with predictive technology model (PTM) model. The simulation results show that the standby power of the PG-adder and PG-counter is only 1.0nW and 3.0 nW, respectively. And the performance of the PG MCML circuits does not deteriorate.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yangbo Wu
AU  - Xiaohui Fan
AU  - Haiyan Ni
AU  - Jianping Hu
PY  - 2013/03
DA  - 2013/03
TI  - Low-Power Near-threshold MOS Current Mode Logic with Power-Gating Techniques
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 1694
EP  - 1697
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.424
DO  - 10.2991/iccsee.2013.424
ID  - Wu2013/03
ER  -