A Buffer Management for STT-MRAM based Hybrid Main Memory in Sensor Nodes

DOI

10.2991/iccnce.2013.71How to use a DOI?

Keywords

Non-volatile memories, Low power, Buffer management, STT-MRAM, NAND flash memory.

Abstract

As the power dissipation has become one of the critical design challenges in a sensor network environment, non-volatile memories such as STT-MRAM and flash memory will be used in the next generation sensor nodes. In this paper, we studied an efficient buffer management scheme considering the write limitation of STT-MRAM based main memory as well as the erase-before-write limitation of flash memory for storage device. The goal of proposed scheme is to minimize the number of write operations on STT-MRAM as well as the number of erase operations on flash memory. We showed through simulation that proposed scheme outperforms legacy buffer management schemes.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Soohyun Yang
AU  - Yeonseung Ryu
PY  - 2013/07
DA  - 2013/07
TI  - A Buffer Management for STT-MRAM based Hybrid Main Memory in Sensor Nodes
BT  - Proceedings of the International Conference on Computer, Networks and Communication Engineering (ICCNCE 2013)
PB  - Atlantis Press
SP  - 286
EP  - 289
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccnce.2013.71
DO  - 10.2991/iccnce.2013.71
ID  - Yang2013/07
ER  -