Architectures of Delay Line ADC and Delay Cells for Digital DC-DC Converters

DOI

10.2991/eeic-13.2013.1How to use a DOI?

Keywords

delay line; delay cells; ADC

Abstract

A survey and classification of architectures is presented in this paper for delay line ADC and its delay cells targeting digital control of DC-DC converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize occupied area and power consumption, a general architecture is designed, which includes one delay line and thermometer-decode. And a particular example of the delay line ADC is described. The ADC operates at 4 MHz switching frequency and has low power consumption and small area. Experimental results verify the functionality of the designed delay line ADC.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Chuang Wang
AU  - Zunchao Li
AU  - Yuanfa Wang
AU  - Zhicong Miao
PY  - 2013/12
DA  - 2013/12
TI  - Architectures of Delay Line ADC and Delay Cells for Digital DC-DC Converters
BT  - Proceedings of the 3rd International Conference on Electric and Electronics
PB  - Atlantis Press
SP  - 1
EP  - 4
SN  - 1951-6851
UR  - https://doi.org/10.2991/eeic-13.2013.1
DO  - 10.2991/eeic-13.2013.1
ID  - Wang2013/12
ER  -