A design method for digital phase-locked loop

DOI

10.2991/nceece-15.2016.263How to use a DOI?

Keywords

phase-locked loop; FPGA; digital processing; algorithm optimization;coherent demodulation

Abstract

The design method of the digital phase-locked loop is presented according to the parameters of the center frequency, the loop filter bandwidth, etc. The modules phase detector(PD), loop filter(LF), voltage controlled oscillator(VCO) have the similar behavior with that of the analog phase-locked loop(APLL) by using Laplace transform and bilinear transformation. For the case of lacking QuartusII license for numerical controlled oscillator(NCO) IP core, It can be replaced by the module designed by using triangle transform which is high-precision. Since enormous numbers of LEs in FPGA will be occupied by the multiplier of filters, the optimization algorithmis presented utilizingaddition operation and shifting operation rather than multiply operation, which reduces resources used on the system. The design result is simulated and realized on FPGA development board, which confirms that the design method is feasible.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Jiyuan Ru
AU  - Yujia Liu
AU  - Wei Xue
PY  - 2015/12
DA  - 2015/12
TI  - A design method for digital phase-locked loop
BT  - Proceedings of the 2015 4th National Conference on Electrical, Electronics and Computer Engineering
PB  - Atlantis Press
SP  - 1471
EP  - 1475
SN  - 2352-5401
UR  - https://doi.org/10.2991/nceece-15.2016.263
DO  - 10.2991/nceece-15.2016.263
ID  - Ru2015/12
ER  -