Hardware Implementation of Rate Control for Motion JPEG2000

DOI

10.2991/nceece-15.2016.71How to use a DOI?

Keywords

Motion JPEG2000; Rate control; Scene change detection; Tier1 coding; FPGA

Abstract

This paper presents a hardware implementation of rate control system with scene change detection for constant bit rate traffic of Motion JPEG2000. The input frames are divided into groups, each group contains one key frame, and a frame which originally is not a key frame of a group is changed to a key frame of a new group according to the result of the scene change detection. The frames are then encoded by Tier1 coding, the bit rate of the key frame in a group is allocated independently, and the bit rates of other frames in a group are allocated by rate distortion slope estimation. The bit streams are then truncated and outputted. The Verilog HDL modules for the architecture are designed, simulated and synthesized to Altera’s FPGA. The result shows that the architecture proposed in this paper is correct.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yang Shijie
PY  - 2015/12
DA  - 2015/12
TI  - Hardware Implementation of Rate Control for Motion JPEG2000
BT  - Proceedings of the 2015 4th National Conference on Electrical, Electronics and Computer Engineering
PB  - Atlantis Press
SP  - 359
EP  - 364
SN  - 2352-5401
UR  - https://doi.org/10.2991/nceece-15.2016.71
DO  - 10.2991/nceece-15.2016.71
ID  - Shijie2015/12
ER  -