A new processor design based on 3D cache

DOI

10.2991/nceece-15.2016.53How to use a DOI?

Keywords

Three-dimensional integration technology; TSV; 3D cache; 3D processor

Abstract

The interconnection is becoming one of main concerns in current and future microprocessor designs from both performance and consumption. Three-dimensional integration technology, with its capability to shorten the wire length, is a promising method to solve issues related the interconnection. In this paper, we propose a new processor architecture based on 3D cache. We integrate 3D cache with the processor which reduces the global interconnection, power consumption and improves access speed. In addition, we simulate the performance of the 3D processor and 3D cache at different node using 3D Cacti tools. Comparing with 2D, the results show power consumption of the memory system is reduced by about 50%, access time and cycle time of the processor increase 18.57% and 21.41%, respectively.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Shan Lei
AU  - Liu Guangbao
AU  - Xie Song
PY  - 2015/12
DA  - 2015/12
TI  - A new processor design based on 3D cache
BT  - Proceedings of the 2015 4th National Conference on Electrical, Electronics and Computer Engineering
PB  - Atlantis Press
SP  - 261
EP  - 265
SN  - 2352-5401
UR  - https://doi.org/10.2991/nceece-15.2016.53
DO  - 10.2991/nceece-15.2016.53
ID  - Lei2015/12
ER  -