Design of the key Structure of Convolutional Neural Network Reconfigurable Accelerator Based on ASIC

DOI

10.2991/ncce-18.2018.47How to use a DOI?

Keywords

Convolutional Neural Network, CNN, accelerator, GoogleNet, AlexNet.

Abstract

In this paper, we propose a reconfigurable architecture that supports various convolutional neural networks (CNNs) such as GoogLeNet and AlexNet. The proposed architecture mainly includes 24 parallel PEs (processing engines) for image data convolution processing, each engine containing 9x4 MAC (multiplier-accumulator) units. Through the combination of PE, this structure can support a variety of bit-width convolution operations, namely 8bit×8bit, 16bit×8bit, 16bit×16bit. At the same time, it also supports a variety of sizes of convolution operation, that is, 1×1, 3×3, 5×5, 7×7. The architecture is synthesized using 65-nm TSMC technology and achieves a peak of 1105.9 GOPS at 640MHz, 1V, and a power consumption of 193mW. Compared with the existing AlexNet architecture, the proposed architecture improves the computational efficiency by 20% to 27.4%.

Copyright

© 2018, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Hongli Pan
AU  - Mingjiang Wang
AU  - Jingqun Li
PY  - 2018/05
DA  - 2018/05
TI  - Design of the key Structure of Convolutional Neural Network Reconfigurable Accelerator Based on ASIC
BT  - Proceedings of the 2018 International Conference on Network, Communication, Computer Engineering (NCCE 2018)
PB  - Atlantis Press
SP  - 301
EP  - 304
SN  - 1951-6851
UR  - https://doi.org/10.2991/ncce-18.2018.47
DO  - 10.2991/ncce-18.2018.47
ID  - Pan2018/05
ER  -