Design and Implementation of Parallel Pipeline Processor

DOI

10.2991/msmee-17.2017.75How to use a DOI?

Keywords

Design, Parallel Pipeline, Processor

Abstract

In order to further improve the speed of instructions' execution on the basis of the current multi-cycle processor and pipeline processor which is commonly used by MIPS processors, we implemented a simple dual-pipeline processor. To show its superiority, we followed the implementation of this three processors, and then carried out the same test and analysis. The final result indicates that the execution speed of the pipeline processor is 2.837 times fast than the multi-cycle processor, while the dual-pipeline processor is running 32.8% faster than the normal pipeline.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Hongyu Fan
AU  - Hui Zhang
AU  - Nan Jiang
AU  - Dongwei Guo
PY  - 2017/05
DA  - 2017/05
TI  - Design and Implementation of Parallel Pipeline Processor
BT  - Proceedings of the 2017 2nd International Conference on Materials Science, Machinery and Energy Engineering (MSMEE 2017)
PB  - Atlantis Press
SP  - 370
EP  - 374
SN  - 2352-5401
UR  - https://doi.org/10.2991/msmee-17.2017.75
DO  - 10.2991/msmee-17.2017.75
ID  - Fan2017/05
ER  -