3D-Partition: A Design Space Exploration Tool for Three-Dimensional Network-on-Chip

DOI

10.2991/mcae-16.2016.28How to use a DOI?

Keywords

3D NoC; design space exploration; many-core processor design.

Abstract

In this paper, we introduce a compositive model of fabrication cost, network throughput and power consumption, to explore different 3D design options of 3D NoCs. The model allows partition of IPs across different dies in 3D stack. Based on the model an estimation tool, 3D-Partition, is created and validated by comparing its results with those obtained from NIRGAM. Effects of various 3D NoC architectures under different 3D IC partition strategies on cost, throughput and power consumption are explored to demonstrate the utility of the tool. It provides economic and performance reference to designing 3D ICs for volume production in the future.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Ji Wu
PY  - 2016/07
DA  - 2016/07
TI  - 3D-Partition: A Design Space Exploration Tool for Three-Dimensional Network-on-Chip
BT  - Proceedings of the 2016 International Conference on Mechatronics, Control and Automation Engineering
PB  - Atlantis Press
SP  - 115
EP  - 118
SN  - 2352-5401
UR  - https://doi.org/10.2991/mcae-16.2016.28
DO  - 10.2991/mcae-16.2016.28
ID  - Wu2016/07
ER  -