LDPC Encoder Design and FPGA Implementation in Deep Space Communication

DOI

10.2991/lemcs-14.2014.81How to use a DOI?

Keywords

Deep Space Communicatio;CCSDS;LDPC;FPGA

Abstract

According to the requirements of deep space communication channel coding and referring to the standard parameters of Consultative Committee for Space Data Systems (CCSDS), a high rate LDPC code scheme set for deep space communications is adopted.[1][2] Due to the Low density parity check (LDPC) codes’ excellent error performance, it’s necessary for Field Programmable Gate Array(FPGA) to achieve CCSDS-LDPC coding. In this context, the serial encoding of CCSDS deep space communication standard (1536,1024) LDPC code is realized on the Xilinx company's XC5VSX100 chip. More specifically, the details of the encoding process is shown in this context. This design can be applied to other rate of LDPC codec based upon deep space communication standard which is set by CCSDS flexibly.

Copyright

© 2014, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Lei Cheng
AU  - Hongpeng Zhu
AU  - Guangxia Li
AU  - Lei Yang
PY  - 2014/05
DA  - 2014/05
TI  - LDPC Encoder Design and FPGA Implementation in Deep Space Communication
BT  - Proceedings of the International Conference on Logistics, Engineering, Management and Computer Science
PB  - Atlantis Press
SP  - 343
EP  - 346
SN  - 1951-6851
UR  - https://doi.org/10.2991/lemcs-14.2014.81
DO  - 10.2991/lemcs-14.2014.81
ID  - Cheng2014/05
ER  -