Speedup Factor Estimation through Dynamic Behavior Analysis for FPGA

DOI

10.2991/jcis.2008.17How to use a DOI?

Keywords

performance event counter, speedup estimation

Abstract

In reconfigurable platform, before convert and download program into real hardware, reliable estimation of speedup factor is of great importance for task schedulers. In this paper, a novel technique for speedup factor estimation is proposed. From the event patterns collected by hardware counters built in modern processors, a formula is given to estimate speedup factor of target process. Experiments on programs from SPEC2006 show that the speedup feature is able to be estimated at an acceptable cost.

Copyright

© 2008, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Zhongda Yuan
AU  - Jinian Bian
AU  - Qiang Wu
AU  - Oskar Mencer
PY  - 2008/12
DA  - 2008/12
TI  - Speedup Factor Estimation through Dynamic Behavior Analysis for FPGA
BT  - Proceedings of the 11th Joint Conference on Information Sciences (JCIS 2008)
PB  - Atlantis Press
SP  - 100
EP  - 104
SN  - 1951-6851
UR  - https://doi.org/10.2991/jcis.2008.17
DO  - 10.2991/jcis.2008.17
ID  - Yuan2008/12
ER  -