A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes

DOI

10.2991/jcis.2006.20How to use a DOI?

Keywords

lifting, discrete wavelet transform

Abstract

In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp.

Copyright

© 2006, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Chin-Fa Hsieh
AU  - Tsung-Han Tsai
AU  - Neng-Jye Hsu
AU  - Chih-Hung Lai
PY  - 2006/10
DA  - 2006/10
TI  - A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes
BT  - Proceedings of the 9th Joint International Conference on Information Sciences (JCIS-06)
PB  - Atlantis Press
SP  - 82
EP  - 85
SN  - 1951-6851
UR  - https://doi.org/10.2991/jcis.2006.20
DO  - 10.2991/jcis.2006.20
ID  - Hsieh2006/10
ER  -