Design and Realization of Multi-port Register File based on Schematic

DOI

10.2991/itms-15.2015.336How to use a DOI?

Keywords

Multi-port register file; Schematic; Programmable Logic Device; FPGA

Abstract

In cpu design, the register file is a necessary device which save the instruction and data. In this paper, we propose a design method for multi-port register file design in the environment of single-cycle CPU system based on the MIPS instruction set and according to the characteristics of multi-port register file, and the Schematic is introduced in order to speed up the development cycle. Furthermore, we discuss the consideration and operational principle of design and realization in detail. The simulation results for the part constructed by FPGA are also presented. In this example which provides the learning and design innovation for other circuit designed.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Lihua Jiang
AU  - Shigao Li
PY  - 2015/11
DA  - 2015/11
TI  - Design and Realization of Multi-port Register File based on Schematic
BT  - Proceedings of the 2015 International Conference on Industrial Technology and Management Science
PB  - Atlantis Press
SP  - 1373
EP  - 1376
SN  - 2352-538X
UR  - https://doi.org/10.2991/itms-15.2015.336
DO  - 10.2991/itms-15.2015.336
ID  - Jiang2015/11
ER  -