Design and implementation of a large points FFT acceleration unit in multi-processor system based on FPGA

DOI

10.2991/isccca.2013.209How to use a DOI?

Keywords

FFT, FPGA, Radix-2, DIT-FFT, Multi-processor, software and hardware co verification.

Abstract

This paper introduces the design and implementation of a large points FFT acceleration unit of multi-processor system based on FPGA. It introduces radix-2 DIT-FFT algorithm and the features of hardware platform. It analyzes the FFT acceleration unit overall and divides it into several modules. Then hardware implementations of modules are discussed. The whole FFT acceleration unit is a part of one multi-processor image processing system and the whole system is tested by software and hardware co verification. Results are verified between the software simulation and Virtex6 evaluation board of Xilinx Company. The results are compatible in the range of error. The FFT acceleration unit meets the needs of the whole system and the design is successful.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Duo-li Zhang
AU  - Xue-peng Yang
AU  - Yu-kun Song
PY  - 2013/02
DA  - 2013/02
TI  - Design and implementation of a large points FFT acceleration unit in multi-processor system based on FPGA
BT  - Proceedings of the 2nd International Symposium on Computer, Communication, Control and Automation (ISCCCA 2013)
PB  - Atlantis Press
SP  - 830
EP  - 833
SN  - 1951-6851
UR  - https://doi.org/10.2991/isccca.2013.209
DO  - 10.2991/isccca.2013.209
ID  - Zhang2013/02
ER  -