Design Phase Locked Loop Accuracy towards Femtosecond Magnitude

DOI

10.2991/ipemec-15.2015.59How to use a DOI?

Keywords

Wireless; Circuit; Design

Abstract

This paper studies the frequency synthesis for precision time protocol clock generation circuit, and more particularly focused on a multi-rate phase locked loop structure for generating an output signal at a desired frequency with reduced jitter towards the magnitude of femtosecond. We proposed a unique structured model that makes use of a multiple rate digital filter to match the noise spectrum characteristics of both input digital controlled oscillator reference and output voltage controlled oscillator respectively. The simulation for two rate case is carried out. This concept can be extended to more than two rates to match with additional noise sources’ spectrum from the other devices such as fractional divider, etc.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Wendi Liu
AU  - Hong X. Qian
AU  - Jun S. Huang
AU  - Qi Chen
PY  - 2015/05
DA  - 2015/05
TI  - Design Phase Locked Loop Accuracy towards Femtosecond Magnitude
BT  - Proceedings of the 2015 International Power, Electronics and Materials Engineering Conference
PB  - Atlantis Press
SP  - 302
EP  - 305
SN  - 2352-5401
UR  - https://doi.org/10.2991/ipemec-15.2015.59
DO  - 10.2991/ipemec-15.2015.59
ID  - Liu2015/05
ER  -