Hardware Accelerating Design Of Image Matching With FNCC Similarity Measure Algorithm

DOI

10.2991/icwcsn-16.2017.23How to use a DOI?

Keywords

component; similarity measure; FNCC; image matching; memory controller structure

Abstract

Similarity measure is a usual image processing algorithm, which is decisive for the quality of image registration. And Fast Normalized Cross Correlation(FNCC) is one of the most common similarity matching algorithm. However, it is computationally intensive and very time consuming which limits its application. This paper presents a hardware accelerating design of similarity measure algorithm using FNCC based on FPGA which is highly faster than DSP solution. The FPGA implementation is performed effectively according to formula deformation, optimized pipelining and parallel processing. And a new memory controller structure which supports mis-aligned access in different bit-width is designed. Compared to the implement on DSP which running at 300MHz, implement on FPGA which works at 100MHz improves the process speed more than an order of magnitude.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xiong-Bo Zhao
AU  - Song-Ling Wu
AU  - Liang-Liang Liu
PY  - 2016/12
DA  - 2016/12
TI  - Hardware Accelerating Design Of Image Matching With FNCC Similarity Measure Algorithm
BT  - Proceedings of the 3rd International Conference on Wireless Communication and Sensor Networks (WCSN 2016)
PB  - Atlantis Press
SP  - 105
EP  - 108
SN  - 2352-538X
UR  - https://doi.org/10.2991/icwcsn-16.2017.23
DO  - 10.2991/icwcsn-16.2017.23
ID  - Zhao2016/12
ER  -