Design of a 24 GHz Programmable Frequency Divider in 65-nm CMOS Process

DOI

10.2991/icmt-13.2013.225How to use a DOI?

Keywords

frequency divider; programmable frequency divider; divide-by-2, prescaler; pulse-swallow counter;

Abstract

A 24 GHz programmable frequency divider in 65-nm CMOS process is presented in this paper. The divide ratio can be varied from 208 to 270 in a step size of 2.The divider consists of a divide-by-2, an 8/9 dual-modulus prescaler, a programmable pulse-swallow counter and a buffer. The post simulation results demonstrate that the divider can operate with the input frequency ranging from 16 GHz to 32 GHz while it draws 7.3 mA from a 1.2 V power supply.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Bao Huagui
AU  - Li Zhiqun
AU  - Li Qin
AU  - Wang Zhigong
PY  - 2013/11
DA  - 2013/11
TI  - Design of a 24 GHz Programmable Frequency Divider in 65-nm CMOS Process
BT  - Proceedings of 3rd International Conference on Multimedia Technology(ICMT-13)
PB  - Atlantis Press
SP  - 1855
EP  - 1862
SN  - 1951-6851
UR  - https://doi.org/10.2991/icmt-13.2013.225
DO  - 10.2991/icmt-13.2013.225
ID  - Huagui2013/11
ER  -