Eliminate the X-Optimization during RTL Verification

DOI

10.2991/icmra-15.2015.75How to use a DOI?

Keywords

X-Optimization;Verification

Abstract

Verification of complex SoC designs suffers from X-optimization issues that often conceal design bugs. The deployment of low power techniques such as power-shutdown in today’s SoC designs exacerbate these X-optimism issues. To address these problems we adopted a new simulation semantic that more accurately models non-deterministic values in logic simulation. In this paper we discuss how to eliminate the X-optimism during RTL verification.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xu Huang
AU  - He Xin
AU  - Lintao Liu
AU  - Luncai Liu
PY  - 2015/04
DA  - 2015/04
TI  - Eliminate the X-Optimization during RTL Verification
BT  - Proceedings of the 3rd International Conference on Mechatronics, Robotics and Automation
PB  - Atlantis Press
SP  - 381
EP  - 385
SN  - 2352-538X
UR  - https://doi.org/10.2991/icmra-15.2015.75
DO  - 10.2991/icmra-15.2015.75
ID  - Huang2015/04
ER  -