Research on a novel Dual-Base Transistor (DUBAT) in 0.5 m Standard Si-base CMOS Process

DOI

10.2991/icmmcce-15.2015.583How to use a DOI?

Keywords

Dual-Base Transistor, CMOS, Negative Resistance Device (NRD), Hybrid Mode Lateral Bipolar Transistor, peak-to-valley current ratio (PVCR)

Abstract

A novel Dual-Base Transistor (DUBAT) having a negative-resistance characteristic is presented. This device contains a lateral p-n-p Bipolar-Junction-Transistor (BJT) and a Hybrid-Mode Transistor, and is fabricated on silicon based 0.5 m CMOS process, compatible with the standard CMOS technology as distinct from the traditional DUBAT. The structure of BJT and the Hybrid-Mode Transistor is self-designed to have better current enhancement, didn’t use the standard component models provided by the process. The total size of the device is 20.55 m×6.72 m. The experimental results demonstrates that the average value of the negative resistance is about -1.04 k , the DUBAT has a low valley current of 20.5970 A, a high peak current of 1.2576 mA and a peak-to-valley current ratio of 61.06. The I-V characteristic of the device is also discussed in the paper.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yan Chen
AU  - Changlong Liu
AU  - WeiLian Guo
PY  - 2015/12
DA  - 2015/12
TI  - Research on a novel Dual-Base Transistor (DUBAT) in 0.5 m Standard Si-base CMOS Process
BT  - Proceedings of the 4th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering 2015
PB  - Atlantis Press
SN  - 2352-538X
UR  - https://doi.org/10.2991/icmmcce-15.2015.583
DO  - 10.2991/icmmcce-15.2015.583
ID  - Chen2015/12
ER  -