A low-complexity decoder based on LDPC

DOI

10.2991/icmit-16.2016.51How to use a DOI?

Keywords

LDPC;low-complexity;FPGA

Abstract

This paper designs a low-complexity decoder based on LDPC of GPS standards.In the design ,the decoder we only uses a CNU(Check Node Unit) in the decoding process,which reduce the hardware sources effectively.Besides,we decreases the decoding complexity through the check matrix equivalence transformation,At last ,we realize the decoder based on Xilinx Kintex7 XC7K325T FPGA.The result suggests that the resources only consumes 124 slices after the software ISE layout and wire.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Feilong Yun
AU  - Hongpeng Zhu
AU  - Feng Du
AU  - Jing Lv
PY  - 2016/04
DA  - 2016/04
TI  - A low-complexity decoder based on LDPC
BT  - Proceedings of the 2016 3rd International Conference on Mechatronics and Information Technology
PB  - Atlantis Press
SP  - 292
EP  - 296
SN  - 2352-538X
UR  - https://doi.org/10.2991/icmit-16.2016.51
DO  - 10.2991/icmit-16.2016.51
ID  - Yun2016/04
ER  -