SLink: An Efficient Point-to-Point Protocol for Chip-to-Chip Interconnection

DOI

10.2991/iceeecs-16.2016.167How to use a DOI?

Keywords

point-to-point protocol; low latency; high bandwidth; FPGA prototype

Abstract

Multi-chip architectures have been a focal point not only in high-performance computing but also in the new generation of embedded systems. For point-to-point topology, high latency and low bandwidth are always found in existing chip-to-chip protocols. This prevents the efficiency of information communication in mutli-chip system. In this paper, we propose a novel low-latency, low-cost and high-scalability protocol, named SLink. We provide an implementation, including the programming model, the simulation and FPGA prototype verification environment. Compared to PCIe 2.0, the results of experiments demonstrate that the latency decreases by 61.0 percent; the maximum bandwidth increases by 55.6 percent and the area decreases by 97.5 percent.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Peinan Li
AU  - Ping Xue
AU  - Chen Lin
AU  - Yinping Jiang
AU  - Hongyu Meng
PY  - 2016/12
DA  - 2016/12
TI  - SLink: An Efficient Point-to-Point Protocol for Chip-to-Chip Interconnection
BT  - Proceedings of the 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)
PB  - Atlantis Press
SP  - 862
EP  - 869
SN  - 2352-538X
UR  - https://doi.org/10.2991/iceeecs-16.2016.167
DO  - 10.2991/iceeecs-16.2016.167
ID  - Li2016/12
ER  -