Research on the Cache Performance Optimization Technology of Multi-Core Processor Chip

DOI

10.2991/iceeecs-16.2016.49How to use a DOI?

Keywords

Cache, Performance Optimization Technology, Multi-Core Processor Chip

Abstract

In the dual drive of process and application, multi-core structure has become the current trend of high-performance microprocessors. The competition of multi-core single-chip limited cache and bandwidth will further highlight the bottleneck of memory access. With the development of multi-target application, the performance evaluation environment of micro-architecture is facing new demands. This paper focuses on the multi-core processor on-chip cache performance optimization technology.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Su Zhang
PY  - 2016/12
DA  - 2016/12
TI  - Research on the Cache Performance Optimization Technology of Multi-Core Processor Chip
BT  - Proceedings of the 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)
PB  - Atlantis Press
SP  - 218
EP  - 221
SN  - 2352-538X
UR  - https://doi.org/10.2991/iceeecs-16.2016.49
DO  - 10.2991/iceeecs-16.2016.49
ID  - Zhang2016/12
ER  -