Design of code error detector based on FPGA

DOI

10.2991/iceeecs-16.2016.6How to use a DOI?

Keywords

code error detector; FPGA; code error detection principle; M sequence; VHDL hardware description language;ÿ

Abstract

With the development of social productivity and the improvement of people's living standard, the development of modern computer technology is more and more fast. In the communication system, the code error detector is the important equipment to detect reliability of communication system, and the traditional code error detector is based on collaborative work of CPLD and CPU[1], not only is the structure complex, expensive, but it is inconvenient to carry. Code error detector based on FPGA, using FPGA to complete the integration of design of control and test module, to improve the scalability and integration of the system. This paper is based on principle of M sequence generation and code error detection, using the VHDL hardware description language, to realize the design of a simple bit by bit comparison code error detector and the simulation of each function module.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Can Zhao
AU  - Jun Yang
AU  - Mengjiao Wu
AU  - Xintao Huang
PY  - 2016/12
DA  - 2016/12
TI  - Design of code error detector based on FPGA
BT  - Proceedings of the 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)
PB  - Atlantis Press
SP  - 22
EP  - 25
SN  - 2352-538X
UR  - https://doi.org/10.2991/iceeecs-16.2016.6
DO  - 10.2991/iceeecs-16.2016.6
ID  - Zhao2016/12
ER  -