Design of a High Definition Video Communication System in Real-time Network

DOI

10.2991/iccsee.2013.565How to use a DOI?

Keywords

FPGA, H.264, ITU-R BT.1120, Low latency,

Abstract

This paper presents the design of a high definition video communication system with real-time performance in the network. In order to process and transmit the high definition video, the design combines FPGA and SOC, follows the H.264 video coding compression. The FPGA realizes the high–speed video acquisition via Cameralink interface, and convert the raw image to ITU-R BT.1120 stream. The SOC contains CPU and Codec, it compresses the BT.1120 stream to H.264 steam and transmit the stream in the network. The low-delay rate control algorithm can limit the bitrate in a very low level. The result shows that the system reduces bandwidth and lowers the latency, the design is adaptable to the real time environments.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yunfeng Liu
AU  - Xianrong Peng
AU  - Zheng Jin
PY  - 2013/03
DA  - 2013/03
TI  - Design of a High Definition Video Communication System in Real-time Network
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 2254
EP  - 2257
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.565
DO  - 10.2991/iccsee.2013.565
ID  - Liu2013/03
ER  -