Improvements of RSA algorithm for hardware encryption implementation based on FPGA

DOI

10.2991/iccsee.2013.10How to use a DOI?

Keywords

Montgomery modular multiplication algorithm, Exclusive or arithmetic unit, RSA algorithm, shift arithmetic unit

Abstract

In the field of information security, encryption and decryption operations in RSA cryptographic algorithm are both modular exponentiation. The direct computing method to implement this algorithm through software programming is to multiply M e times with iteration statements and later make modulo operations. The operational speed of this method is feasible when M, e and n are relatively small. However, in order to enhance the security of RSA algorithm, we need to take at least 512-bit values for M, e and n. The operation speed in the way of software implementation is slow, and intermediate results will also take up lots of temporary storage space. Thus, software implementation has great difficulties. In contrast, hardware encryption has high security, fast speed and strong real-time property. At present, FPGA-based RSA hardware encryption and decryption is a new research direction, and an improved study on the existing low-radix Montgomery algorithm has been made in this article.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Youguo Li
PY  - 2013/03
DA  - 2013/03
TI  - Improvements of RSA algorithm for hardware encryption implementation based on FPGA
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 38
EP  - 41
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.10
DO  - 10.2991/iccsee.2013.10
ID  - Li2013/03
ER  -