An on-Chip Clock Controller for Testing Fault in System on Chip

DOI

10.2991/iccsee.2013.1How to use a DOI?

Keywords

at-speed scan test, on-chip clock, transition-delay faults, phase-locked loop

Abstract

In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase-locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timing-related defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Wei Lin
AU  - Wen-Long Shi
PY  - 2013/03
DA  - 2013/03
TI  - An on-Chip Clock Controller for Testing Fault in System on Chip
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 1
EP  - 4
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.1
DO  - 10.2991/iccsee.2013.1
ID  - Lin2013/03
ER  -