FinFET Technology based Low Power SRAM Cell Design for Embedded Memory

DOI

10.2991/978-94-6463-471-6_106How to use a DOI?

Keywords

6T SRAM; Cadence Virtuoso; MOSFET; Efficiency; Standby leakage current; FinFET

Abstract

Computer systems rely heavily on cache memory because it offers a quicker and more effective means of accessing frequently used data. It serves as a buffer between the CPU (central processing unit) and main memory (RAM). Electronic devices’ energy use during standby or idle mode is referred to as standby leakage, standby power consumption, or vampire power. This is a significant concern because it results in unnecessary energy wastage and can contribute to higher electricity bills and increased environmental impact. Low-energy techniques are crucial in minimizing current leakage and improving the energy efficiency of electronic devices. Current leakage, also known as leakage current or sub threshold leakage, refers to the unintended flow of current in transistors and other components even when they are in an off or standby state. This leakage current can contribute significantly to power consumption and reduce the overall energy efficiency of devices. Designing a 6T SRAM cell using FinFET technology at the 18nm process node involves creating a layout and optimizing the circuit for performance and efficiency.6T SRAM cell using FinFET technology at the 18nm process node requires a deep understanding of circuit design, layout techniques, and semiconductor physics. The goal is to achieve a balance between performance, stability, power consumption, and manufacturability to create an efficient and reliable memory cell. FinFETs offer improved gate control, reduced leakage current, enhanced performance, and better power efficiency compared to traditional planar transistors. These features make FinFET technology a electronic cornerstone of modern semiconductor design, enabling the development of high-performance, energy-efficient devices.

Copyright

© 2024 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Jami Venkata Suman
AU  - Mamidipaka Hema
AU  - A. Swetha Priya
AU  - D. Raja Ramesh
AU  - Patna Syamala Devi
AU  - Subba Rao Polamuri
PY  - 2024
DA  - 2024/07/30
TI  - FinFET Technology based Low Power SRAM Cell Design for Embedded Memory
BT  - Proceedings of the International Conference on Computational Innovations and Emerging Trends (ICCIET- 2024)
PB  - Atlantis Press
SP  - 1116
EP  - 1124
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-471-6_106
DO  - 10.2991/978-94-6463-471-6_106
ID  - Suman2024
ER  -