A System Design for DSP + FPGA Based Cache-structured Image Processing

DOI

10.2991/iccasm.2012.319How to use a DOI?

Keywords

Image processing driver, overtime, cache structure

Abstract

This essay presents the DSP + FPGA structure based high-performance image processing system. It aims at solving the overtime-processing problem brought by the increasing complexity of images through the cache-structured image-processing driver. This system allows frame-dropping whenever the processing of images runs overtime and achieves one frame. The system simulation result shows in this way the diver achieves higher efficiency than traditional ping-pong mode when dealing with the overtime-processing of images.

Copyright

© 2012, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Jinhua Liu
AU  - Shuang Zhang
AU  - Shu Li
AU  - Jing Xiao
PY  - 2012/08
DA  - 2012/08
TI  - A System Design for DSP + FPGA Based Cache-structured Image Processing
BT  - Proceedings of the 2012 International Conference on Computer Application and System Modeling (ICCASM 2012)
PB  - Atlantis Press
SP  - 1252
EP  - 1255
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccasm.2012.319
DO  - 10.2991/iccasm.2012.319
ID  - Liu2012/08
ER  -