The IP-core Design of Controller and F/F' Transformer in High-speed and Low-cost SM4 Chip

DOI

10.2991/icaset-18.2018.40How to use a DOI?

Keywords

Controller, F/F' conversion module, SM4 chip

Abstract

The single cycle structure with a small area is difficult to encrypting high-speed SM4 streams in real time, while fully pipelined design is not available for the system's application in low-cost areas. Aiming at this, the pipeline method and the single cycle scheme are combined to build a high-speed and low-cost SM4 chip. At first, the common of the key expansion and encryption algorithm are compared, and then a multifunctional F/F' transformation module are present in detail. The designed IP core can be applied to each of the key expansion, encryption and decryption modules. At second, the startup module and data-path module are separated, and the feedback for iterative signal and serials of numbering mechanisms are set. Therefore a high-speed control module is designed, which can timely start every operation module to streamline the work efficiently. Finally, based on the FPGA simulation, it is seen that the designed controller can promptly manage the encryption system and the soft core of F/F' conversion can be easily transplanted to all types of SM4 system. So it's quite promising in broad market.

Copyright

© 2018, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Qian Lv
AU  - Li Li
AU  - Yan-yan Cao
PY  - 2018/04
DA  - 2018/04
TI  - The IP-core Design of Controller and F/F' Transformer in High-speed and Low-cost SM4 Chip
BT  - Proceedings of the 2018 8th International Conference on Applied Science, Engineering and Technology (ICASET 2018)
PB  - Atlantis Press
SP  - 196
EP  - 202
SN  - 2352-5401
UR  - https://doi.org/10.2991/icaset-18.2018.40
DO  - 10.2991/icaset-18.2018.40
ID  - Lv2018/04
ER  -