A 14-b 500 MSPS Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration

DOI

10.2991/ic3me-15.2015.179How to use a DOI?

Keywords

A/D converter, time-interleaved ADC, digital calibration.

Abstract

This paper presents a 14-bit 500MSPS ADC in 0.18 um CMOS process. By interleaving two 250MSPS ADCs, a sample rate of 500MSPS is achieved. The offset, gain error and time skew between the two channels are calibrated in the background. The measurement shows that the ADC has performances of 10.6 bits ENOB, 78dBc SFDR, 4 by 4 square micrometers area and 950mW power consumption under power supply of 1.8V.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xingfa Huang
AU  - Dongbing Fu
AU  - Rongbin Hu
AU  - Jie Pu
AU  - Xiaofeng Shen
AU  - Jing Li
AU  - Liang Li
PY  - 2015/08
DA  - 2015/08
TI  - A 14-b 500 MSPS Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration
BT  - Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering
PB  - Atlantis Press
SP  - 934
EP  - 937
SN  - 2352-5401
UR  - https://doi.org/10.2991/ic3me-15.2015.179
DO  - 10.2991/ic3me-15.2015.179
ID  - Huang2015/08
ER  -