A 12 Bit IF Sampling Pipelined ADC in 0.18um BiCMOS
Authors
Liang Li, Dongbing Fu, Mingyuan Xu, Xingfa Huang
Corresponding Author
Liang Li
Available Online August 2015.
- DOI
- 10.2991/ic3me-15.2015.177How to use a DOI?
- Keywords
- switched capacitor, IF Sampling, input buffer, BiCMOS.
- Abstract
In this paper, a 12 bit 500MS/s IF Sampling ADC is described. The ADC has an integrated input buffer with a new linearization technique that improves its distortion. Eight pipeline stages with fully differential switched capacitor architecture follow the input buffer. Each of stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier(MDAC). A 0.18 m BiCMOS process with 1.8V analog power supply is used in the design. This ADC achieves an SNR of 65dB and an SFDR of 82dB for sampling analog input frequencies up to 250MHz
- Copyright
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Liang Li AU - Dongbing Fu AU - Mingyuan Xu AU - Xingfa Huang PY - 2015/08 DA - 2015/08 TI - A 12 Bit IF Sampling Pipelined ADC in 0.18um BiCMOS BT - Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering PB - Atlantis Press SP - 926 EP - 929 SN - 2352-5401 UR - https://doi.org/10.2991/ic3me-15.2015.177 DO - 10.2991/ic3me-15.2015.177 ID - Li2015/08 ER -