Design of SDRAM Controller IP Core Based on FPGA

DOI

10.2991/emcpe-16.2016.159How to use a DOI?

Keywords

FPGA, SDRAM Controller, IP core, Timing Analysis.

Abstract

Although having advantages of high integration, Low power consumption and strong processing capability, etc., it is not easy for SDRAM to be developed and applied because of its timing complexity. To reduce costs, and shorten the development period, combining with features of strong reconfiguration and portability for the design based on FPGA, particular timing constraints for the read and write processes of SDRAM controller were made and SDRAM controller IP soft core was designed according to SDRAM control norms, using EDA top-down design method. The IP core was verified with Altera's FPGA-EP2C35F484C8 devices. Timing simulation and SignalTapII logic analyzer sampling results show that the designed IP core is in line with SDRAM timing requirements and can operate reliably and continuously. The design has high reliability and universal applicability.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yonggang Chen
AU  - Yawen Li
AU  - Caizhen Zhang
PY  - 2016/08
DA  - 2016/08
TI  - Design of SDRAM Controller IP Core Based on FPGA
BT  - Proceedings of the 2016 5th International Conference on Environment, Materials, Chemistry and Power Electronics
PB  - Atlantis Press
SP  - 626
EP  - 631
SN  - 2352-5401
UR  - https://doi.org/10.2991/emcpe-16.2016.159
DO  - 10.2991/emcpe-16.2016.159
ID  - Chen2016/08
ER  -