A New Method for Reducing the Leakage Current in the Readout Circuit of Ultraviolet Focal Plane Detector

DOI

10.2991/eee-19.2019.8How to use a DOI?

Keywords

Readout circuit, CTIA, Low-Leakage

Abstract

A readout circuit with low leakage current is presented which performs leakage current suppression and integration linearity enhancement. An additional transmission gate is added to suppress the leakage current by forcing each end of MOSFETs in the transmission gate to be equal so that the discharge circuit of integration capacitor can be completely cut off when the integration circuit is at the stage of integration. It is simulated and implemented in a standard 0.18-µm CMOS process. The results show the leakage current is reduced to 1.5 nA which is 4 times lower compared with conventional circuit. The linearity of integration is 99.9% in proposed integration circuit.

Copyright

© 2019, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Chen Zhang
AU  - Xi-ran Zhang
AU  - Wei Zhu
AU  - Hui Zhong
AU  - Yu Shi
PY  - 2019/07
DA  - 2019/07
TI  - A New Method for Reducing the Leakage Current in the Readout Circuit of Ultraviolet Focal Plane Detector
BT  - Proceedings of the 2nd International Conference on Electrical and Electronic Engineering (EEE 2019)
PB  - Atlantis Press
SP  - 41
EP  - 45
SN  - 2352-5401
UR  - https://doi.org/10.2991/eee-19.2019.8
DO  - 10.2991/eee-19.2019.8
ID  - Zhang2019/07
ER  -