A Low Power Fast Locking PLL Frequency Synthesizer with Temperature Compensation

DOI

10.2991/eame-18.2018.59How to use a DOI?

Keywords

PLL; fast locking; temperature compensation

Abstract

A temperature compensated phase-locked loop (PLL) frequency synthesizer with small locking time is presented. The locking speed is improved by combining the methods of direct frequency presetting and dynamic loop bandwidth. A new technique of temperature compensation combining the static temperature compensation and the dynamic temperature compensation is proposed to effectively reduce the variation of the presetting frequency with the temperature, and high precision frequency presetting and fast locking in a wide temperature range are achieved. The proposed PLL frequency synthesizer is implemented in 180nm CMOS process. The simulation results show that the power consumption is 5mA from 1.8V power supply, and the typical locking time is less than 2μs in the temperature range of 0°C~80°C. The output frequency range is 2.1GHz to 2.6GHz, and the phase noise is -117dBc/Hz@1MHz. The designed PLL frequency synthesizer can be widely used in today’s communication systems.

Copyright

© 2018, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Zhiqing Geng
AU  - Xiaojin Ma
AU  - Zuopeng Li
PY  - 2018/06
DA  - 2018/06
TI  - A Low Power Fast Locking PLL Frequency Synthesizer with Temperature Compensation
BT  - Proceedings of the 2018 3rd International Conference on Electrical, Automation and Mechanical Engineering (EAME 2018)
PB  - Atlantis Press
SP  - 281
EP  - 285
SN  - 2352-5401
UR  - https://doi.org/10.2991/eame-18.2018.59
DO  - 10.2991/eame-18.2018.59
ID  - Geng2018/06
ER  -