An Effective Strategy of Area Reduction for Custom Instruction Based on Basic Cell

DOI

10.2991/csss-14.2014.109How to use a DOI?

Keywords

custom instruction, FPGA, area reduction, merging

Abstract

Area reduction is very important for CI (Custom Instruction) on reconfigurable processor. However, for FPGA (Field Programmable Gate Array) structure, resource sharing method is inefficient for area reduction of data-path. In the paper, we propose an effective strategy of area reduction for custom instruction. Firstly, we partitioned data-path of the final CI to lots of BCs (Basic Cells). Then we checked all the validity of BCs to make sure that each BC can be realized using single logic element of FPGA, and selected the unique BC set to overlap original data-paths. Finally, on the basis of BC partitioning, we adopt an approach of Merging CIs to reduce area cost of data-path, which is different from traditional method of resource sharing. Experiment results show that basic cell can really represent FPGA architecture, compared to a method of efficient resource sharing, the approach of merging CIs based on BC can lead to more than 11% average reduction of area.

Copyright

© 2014, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Liu Haiming
AU  - Ma Yuchun
AU  - Wu Qiang
PY  - 2014/06
DA  - 2014/06
TI  - An Effective Strategy of Area Reduction for Custom Instruction Based on Basic Cell
BT  - Proceedings of the 3rd International Conference on Computer Science and Service System
PB  - Atlantis Press
SP  - 465
EP  - 468
SN  - 1951-6851
UR  - https://doi.org/10.2991/csss-14.2014.109
DO  - 10.2991/csss-14.2014.109
ID  - Haiming2014/06
ER  -