A Resource Efficient Decoder for Polar Code Based on FPGA

DOI

10.2991/978-94-6463-108-1_86How to use a DOI?

Keywords

polar code; low resource consumption; successive cancellation list decoding; FPGA implementation

Abstract

A resource efficient hardware implementation method of polar decode is presented in this paper. It supports the configuration of bit allocation table with various code lengths and rates. The hardware implementation based on Successive Cancellation List Decoding (SCL) scheme makes BER (Bit-Error-Rate) performance more excellent, and the pipe-lined and paralleled design achieved a good balance between performance and complexity, maintaining a high throughput while consuming less resources. The method is implemented on FPGA and has excellent performance. Compared with other hardware implementation methods, the method can achieve the same throughput with less hardware resource.

Copyright

© 2022 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Chenguang Yang
AU  - Huibin Zhang
PY  - 2022
DA  - 2022/12/30
TI  - A Resource Efficient Decoder for Polar Code Based on FPGA
BT  - Proceedings of the 2022 International Conference on Computer Science, Information Engineering and Digital Economy (CSIEDE 2022)
PB  - Atlantis Press
SP  - 774
EP  - 781
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-108-1_86
DO  - 10.2991/978-94-6463-108-1_86
ID  - Yang2022
ER  -