An 1GHz~6.25GHz Phase-Locked Loop for SERDES

DOI

10.2991/cnci-19.2019.17How to use a DOI?

Keywords

PLL, SERDES, adaptive bandwidth, acquisition speed, jitter performance.

Abstract

An 1GHz~6.25GHz phase-locked loop (PLL) for SERDES is presented in this paper. For achieving optimized balance between acquisition speed and jitter performance at all frequency points, this PLL adopts an adaptive bandwidth method. A current-programmable charge pump is introduced to make loop bandwidth configurable. And a novel Current Controller module is used to output configurable codes automatically. This PLL is implemented in 65nm, 1P10M CMOS technology, occupying an area of 0.17mm2. Results show its charge pump can draw 20uA to 420uA currents from 1.2V supply, proportional to changeable bandwidth 3MHz~58MHz. The measured jitter and locking time at 6.25GHz are 5.52ps and 9.5us, respectively.

Copyright

© 2019, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xuan Ma
AU  - Zongmin Wang
AU  - Tieliang Zhang
AU  - Song Yang,
AU  - Wen Xiao
PY  - 2019/05
DA  - 2019/05
TI  - An 1GHz~6.25GHz Phase-Locked Loop for SERDES
BT  - Proceedings of the 2019 International Conference on Computer, Network, Communication and Information Systems (CNCI 2019)
PB  - Atlantis Press
SP  - 125
EP  - 128
SN  - 2352-538X
UR  - https://doi.org/10.2991/cnci-19.2019.17
DO  - 10.2991/cnci-19.2019.17
ID  - Ma2019/05
ER  -