An Algorithm on Direct Tunneling Current Model Based on DIBL Effect

DOI

10.2991/cmfe-15.2015.171How to use a DOI?

Keywords

Scaled Device; Ultra-Thin Gate Oxide; DIBL; Direct Tunneling Current Model; Static Charateristics

Abstract

With the scaling of NMOS devices, gate tunneling current increases significantly under Drain Induced Barrier Lowering (DIBL), and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory on direct tunneling current predicting model under DIBL is presented in ultra-thin gate oxide NMOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of NMOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Tiefeng Wu
AU  - Zhichao Zhao
AU  - Lizhi Gu
AU  - Quan Wang
AU  - Jing Li
PY  - 2015/07
DA  - 2015/07
TI  - An Algorithm on Direct Tunneling Current Model Based on DIBL Effect
BT  - Proceedings of the International Conference on Chemical, Material and Food Engineering
PB  - Atlantis Press
SP  - 724
EP  - 727
SN  - 2352-5401
UR  - https://doi.org/10.2991/cmfe-15.2015.171
DO  - 10.2991/cmfe-15.2015.171
ID  - Wu2015/07
ER  -