A Low Power Dual Modulus Prescaler
- Abstract
CMOS refers to both, reduction in size and power consumption. Here, the Dual Modulus Prescaler is to be fabricated in 90 nm technology. It basically comprises of AND logic which controls the pulses produced at the output i.e. 1 or 2 pulses that need to be generated at the output, from 256/257 input pulses respectively. The synchronous divide-by-4/5 divider uses symmetric fashion D flip-flops with nMOS gates and the inverters to achieve more than 10 GHz maximum operating frequency. The use of this design will make the consumption of the power in microwatt, as the source couple logic used in the previous design concepts has power consumption in mW [1]. This modules output is to be carried out by using the Micro wind software 3.1. The prescaler will require 1.2-V supply. The prescaler’s estimated operating frequency is upto 17 GHz. Keywords:Dual modulus prescaler, CMOS, low power.
- Copyright
- © 2013, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Nikhil R. Shimpi AU - Shilpa P. Kodgire PY - 2013/04 DA - 2013/04 TI - A Low Power Dual Modulus Prescaler BT - Proceedings of the Conference on Advances in Communication and Control Systems (CAC2S 2013) PB - Atlantis Press SP - 393 EP - 397 SN - 1951-6851 UR - https://www.atlantis-press.com/article/6342 ID - Shimpi2013/04 ER -