Design of 4GHz CMOS Charge-pump Phased-locked Loop based on the Simulink Behavioral Simulation

DOI

10.2991/amee-17.2017.14How to use a DOI?

Keywords

component; Phase-locked loop; Charge pump; Loop parameters; Phase noise

Abstract

According to the basic working principle and the structure analysis of the phase-locked loop, the simulation and analysis of the loop stability with the change of the main loop parameters have been finished according to the established third order dynamic model on the Simulink of the MATLAB, a fast transient simulation method and circuit design theoretical guidance of the charge pump phase-locked loop are provide in the paper. The 4GHz Charge pump phase-locked loop is implemented in the 0.18 m mixed-signal and RF 1P6M CMOS technology of SMIC.The chip area is 0.675 mmž0.700 mm. Based on the design and optimization of the loop parameters, the measured frequency of the VCO is from 3.98GHz to 4.3 GHz when the control voltage is chang from 0.3V to 1.5V, the measured phase noise of the CPLL is -91dBc/Hz at 100 kHz offset and -117 dBc/Hz at 1 MHz offset from the carrier 4.154 GHz under the locked stade.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Lixin Li
AU  - Xiushan Wu
AU  - Jianqiang Han
PY  - 2017/09
DA  - 2017/09
TI  - Design of 4GHz CMOS Charge-pump Phased-locked Loop based on the Simulink Behavioral Simulation
BT  - Proceedings of the 2017 2nd International Conference on Automation, Mechanical and Electrical Engineering (AMEE 2017)
PB  - Atlantis Press
SP  - 70
EP  - 73
SN  - 2352-5401
UR  - https://doi.org/10.2991/amee-17.2017.14
DO  - 10.2991/amee-17.2017.14
ID  - Li2017/09
ER  -