Design of the Image Accelerator Based on FPGA

DOI

10.2991/aeecs-18.2018.54How to use a DOI?

Keywords

FPGA; Hardware acceleration; Image edge detection.

Abstract

This thesis introduces a kind of image accelerator design based on FPGA, Hardware acceleration achieve the purpose of accelerating by increasing operation parallelism, the DMA controller accesse memory, and the DMA controller gives address and control signals, in order to avoid conflict due to multiple main equipment access the memory at the same time, therefore introducting arbitrator (Arbiter), who decided which module to get access to the memory bus control, processing the image through the edge detection accelerator,the experimental results show that it can be real-time and efficiently complete the image processing, it can be applied to the image, video, and other fields.

Copyright

© 2018, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Liang Jia
AU  - Huichao Yang
AU  - Yi Yin
PY  - 2018/03
DA  - 2018/03
TI  - Design of the Image Accelerator Based on FPGA
BT  - Proceedings of the 2018 2nd International Conference on Advances in Energy, Environment and Chemical Science (AEECS 2018)
PB  - Atlantis Press
SP  - 323
EP  - 328
SN  - 2352-5401
UR  - https://doi.org/10.2991/aeecs-18.2018.54
DO  - 10.2991/aeecs-18.2018.54
ID  - Jia2018/03
ER  -